(a) Field of the Invention
The present invention relates to a capacitor structure, more particularly, to a decoupling capacitor (structure) packaged into a multi-layer wiring board mounting thereon a semiconductor element (chip) or electronic parts, requiring a high-speed switching operation, and to a multi-layer wiring board and a semiconductor device into which the capacitor is built respectively.
Here the multi-layer wiring board functions as a package on which the semiconductor element (chip), and the like, are mounted, and thus is also referred to as a “semiconductor package” in the description below, for convenience of explanation.
(b) Description of the Related Art
In the recent semiconductor packages (multi-layer wiring boards) in which a higher density is required, respective wiring patterns are arranged very close to each other. Therefore, such problems may arise that crosstalk noises are generated between wirings, or that potentials of the power supply line, and the like, are varied. In particular, in the package on which a semiconductor element or electronic parts requiring a high-speed switching operation are mounted, the crosstalk noise is easy to happen with an increase in the frequency, and the switching noise also happens because the switching element is turned ON/OFF at high speed. As a result, potentials of the power supply line, and the like, are liable to vary.
Therefore, in the prior art, for the purpose of stabilizing the power supply voltage and reducing the switching noise, or the like, the power supply line, the signal line, or the like, is “decoupled” by attaching a capacitive element such as a chip capacitor or the like, to the package on which semiconductor elements are mounted.
In this case, the margin in design of the wiring patterns is restricted because of the provision of the chip capacitor, otherwise leading distances of the wiring patterns to connect the chip capacitor and power supply/ground terminals of the semiconductor element are lengthened to thereby cause an increase in the inductance. If the inductance is high, the decoupling effect by the capacitor is weakened. Thus, it is desirable that the inductance should be as small as possible. In other words, it is desirable that a capacitive element such as a chip capacitor or the like, should be arranged as close as possible to the semiconductor element.
To cope with this, it may be conceived that, in place of attaching the capacitive element such as the chip capacitor or the like, to the semiconductor package, the equivalent capacitive element (capacitor) is incorporated into the semiconductor package. An example of the case is described in Japanese unexamined Patent Publication (JPP) (Kokai) 11-68319. In the technology recited therein, the decoupling capacitor is incorporated into the multi-layer circuit board made of resin obtained by the built-up process, and the dielectric layer sandwiched between two-layer conductive patterns constituting the capacitor is formed of the material (resin) having the relative dielectric constant of a predetermined value or more. Also, another example is described in JPP (Kokai) 2003-68923. In the technology recited therein, each capacitor portion consists of the wiring layer (one electrode layer) formed on the insulating basic member, the resin layer (dielectric layer) formed on the wiring layer, and the wiring layer (the other electrode layer) formed on the insulating basic member including the resin layer, and then the capacitor obtained by stacking the capacitor portion in a multi-stage manner is incorporated into the semiconductor package.
In the prior art (see JPP 11-68319, JPP 2003-68923) as described above, in order to make the inductance of the decoupling capacitor as small as possible, wiring distances between the capacitor and the semiconductor element to be mounted are reduced as short as possible by incorporating the capacitor into the semiconductor package. In the above prior art, the respective electrodes (conductive patterns, wiring layers) formed on both sides to put the dielectric layer of the capacitor therebetween are connected to a single electrode terminal (external connection terminal). Therefore, when the signal voltage is applied across the electrode terminals, the electric field is generated in one direction between the electrodes according to the polarity of the signal voltage and thus the inductance generated by the current along the direction of the electric field exhibits a certain constant value. In other words, the inductance of the decoupling capacitor has been fixed in dependence on the magnitude of the signal voltage applied across the electrode terminals connected to the respective electrodes of the capacitor on a one-to-one correspondence.
In the state of the art, semiconductor elements, electronic parts, or the like, that are mounted on the package, operate with a high frequency of GHz or more. Thus, the stable operation in the high frequency range of the GHz band is also required of a capacitor used as a decoupling element.
However, in the above prior art, the respective electrodes of the capacitor are connected to the external connection terminals (electrode terminals) on a one-to-one correspondence. Therefore, the problem has arised in that there is a limit to the reduction of the inductance due to the configurative restriction, and thus the above technology cannot always satisfactorily meet the above demand.